§ The E1M™ platform · v1.2

Open edge AI, vendor-neutral.

Modules on Alif, Renesas, and DeepX silicon — two footprints, one contract, pin-compatible within each footprint. One SDK. Hardware engineers and AI builders shouldn't have to choose.

Hardware-agnosticAI-optimisedIndustrial-grade

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§ E1M-X V2N

E1M modules · one SDK

132×

AI compute range

Open, published footprints

Silicon vendors · 1 API

§ Any silicon

Two footprints. One contract. Swap silicon, keep your carrier.

Every module in a footprint family lands on the same pads — swap modules within the family without redesigning your base board. The spec and the SDK span both families.

AlifEnsemble E3–E8 · MCU-class

E1M

35 × 35 mm · 312 pads

pin-compatible within E1M

RenesasRZ/V2N · RZ/V2H · MPU-classDeepXDX-M1 · +M1 companion NPU

E1M-X

45 × 65 mm · 496 pads

pin-compatible within E1M-X

◆ One contract · one SDKsame spec, same <alp/*.h> API across both families

§ E1M™ product line

AI performance that scales with your needs.

From 0.25–0.5 TOPS always-on sensing to 33 TOPS heterogeneous compute — same unified Alp SDK, same C/C++ API, same toolchain. Lower expenses with custom-built SoM options; shape your module to include only the functions that matter.

E1M-AEN

0.25–0.5TOPS · AI

E1M-AEN

MCU+MPU: 2×M55 + opt. A32
NPU: 2× Ethos-U55
Form: 35×35 · 312p
Power: <1 mW always-on

E1M-X

4TOPS · AI

E1M-X V2N

CPU: 4×A55 @ 1.8GHz
NPU: 4 TOPS
Form: 45×65 · 496p
IFC: MIPI·PCIe·USB3

Coming soon

E1M-X

8TOPS · AI

E1M-X V2H

CPU: 4×A55 + 2×R8
NPU: 80 TOPS (sparse)
Form: 45×65 · 496p
IFC: MIPI·PCIe·USB3·2×ETH

E1M-X

29TOPS · AI

E1M-X V2N+M1

CPU: 4×A55 @ 1.8GHz
NPU: 29 TOPS
Form: 45×65 · 496p
IFC: MIPI·PCIe·USB3·2×ETH

Coming soon

E1M-X

33TOPS · AI

E1M-X V2H+M1

CPU: 4×A55 + 2×R8
NPU: 33 TOPS dense
Form: 45×65 · 496p
IFC: MIPI·PCIe·USB3·2×ETH

See all modules ↗Compare side by side ↗

§ Pocket-sized AI

Same compute. A fraction of the footprint.

Drawn to scale relative to each other — what fits where your product needs to go.

1 Euro coin
Ø 23.25 mm
E1M
35 × 35 mm · 312 pads
E1M-X
45 × 65 mm · 496 pads
Raspberry Pi 5
85 × 56 mm
Credit card
85.6 × 54 mm
iPhone 15 Pro
70.6 × 146.6 mm

Drawn to scale relative to each other. Both modules fit in the palm of your hand.

§ Edge AI development · AI modules for robotics

Powering the future of robotics and smart manufacturing.

Smart machines need smart brains. Alp Lab delivers that intelligence through advanced Edge AI hardware — modules that help machines think, work, and react more efficiently in real-world conditions.

Open Standard

Two published footprints that any silicon vendor can build to, with pin-to-pin compatible modules within each footprint. Design the carrier once per footprint.

Unified SDK

One SDK across all modules. Streamline development with consistent APIs and tools.

Industrial Reliability

Built for harsh environments + 10-year minimum supply. Extended temperature, vibration resistance, and a written lifecycle commitment.

Edge AI Performance

Optimized for AI workloads at the edge. Run complex models locally with minimal latency.

§ Portfolio compatibility

Replace what you need. Keep what you trust.

Every module in a footprint family lands on the same pads, so you can move up or down in compute — for example E1M-X V2N to V2H or V2N+M1 — without redesigning the base hardware. Both footprints are published, so any silicon vendor or module maker can build to them.

Flexible Edge AI system-on-module architecture: high-performance compute in a compact design. Small, powerful modules that handle heavy workloads while keeping response times low — ideal for industrial automation and busy factory floors.

See the full standard →

1 carrier · any conformant module

Two footprints, open to any chip

E1M·E1M-X

35×35 mm / 45×65 mm

§ The Alp SDK stack

Write once, run on any E1M module.

One unified C/C++ API across every E1M SoM — Alp SDK wraps each vendor SDK on top of your chosen OS, so a single application builds for Zephyr, Yocto, bare-metal, or any mix.

AI Framework

On-device inference

Ethos-UDRP-AI3DEEPX

TFLM runtime · classification · detection · segmentation · KWS · pose

Dev Tooling

Build, orchestrate, flash

v0.17.0

CodegenValidateFlashEEPROM

board.yaml v2 · per-core emit · tan build / flash / generate · conformance suite

Alp SDK

One unified <alp/*.h> API

PeripheralsAudioCameraInferenceIoT / BLESecurityGUIDSP / Power

unified <alp/*.h> API · 80+ chip drivers · heterogeneous IPC

Operating System

Per-core slice (cores: in board.yaml) · heterogeneous = peers on same SoM

Bare-metal

per-core slice · M-class on Zephyr · A-class on Yocto · no-RTOS bare-metal

Vendor SDK

We wrap each one

one wrapper per vendor — same alp API regardless of silicon

Hardware + HAL

E1M open-standard form factor

E1M 35×35 mmE1M-X 45×65 mmEVK carriersvendor HALs

open-standard form factors · pin-compatible within each footprint

See the full SDK stack →

80+ chip drivers · heterogeneous IPC · per-core OS slices

§ Solutions by industry

Purpose-built edge AI for every vertical.

The best edge AI for robotics, manufacturing, and beyond — enabling machines to see, learn, and move. Built on a proven SoM platform that turns bold ideas into real, working edge AI products.

Drones & UAVs

Autonomous flight, on-device

Real-time AI processing for autonomous flight, object detection, and mission planning — no cloud round-trip.

Read the vertical brief →

Robotics

See, learn, move

AI-powered automation, collaborative robots, and smart robotic systems for modern industry.

Read the vertical brief →

Industrial automation

Inspect, predict, optimize

Visual inspection, predictive maintenance, and process optimization at the edge.

Read the vertical brief →

Agriculture

Precision farming, autonomous

AI-powered crop monitoring and autonomous farm equipment running independently in the field.

Read the vertical brief →

Energy

Real-time grid + solar

Smart grid monitoring, solar tracking, and equipment diagnostics measured at the asset.

Read the vertical brief →

Smart infrastructure

City sensing, privacy-first

People counting, traffic flow, energy monitoring — AI at the sensor, never streams raw video.

Read the vertical brief →

§ E1M™ open standard · v1.2

An open standard, not a walled garden.

The E1M specification fixes the carrier-board pinout, mechanical envelope, and electrical interface of two form factors — 35 × 35 mm (312 pads) and 45 × 65 mm (496 pads). A carrier board built to either footprint hosts any module that conforms to it, whichever silicon is on the module.

Published under CC BY-SA 4.0. Machine-readable pinouts. Third parties welcome.

Read the spec on GitHub ↗Spec overview →

E1M · "Normal"

35 × 35 mm

312 pads · LGA

Ethernet: 2
USB 3.x: 1
MIPI CSI: 2
PCIe 4-lane: 1

Hosts: AEN

E1M-X · "Extended"

45 × 65 mm

496 pads · LGA · + parallel LCD

Ethernet: 2
USB 3.x: 2
MIPI CSI: 4
PCIe 4-lane: 2

Hosts: V2N · V2H · +M1 variants

§ One SDK

One board.yaml. Every module.

Describe the build once. The Alp SDK wraps every vendor's stack under one C/C++ API on Arm CMSIS — switch the SKU and application code written against that API rebuilds for Alif, Renesas, or DeepX silicon. No rewrite.

See the SDK →VS Code extension ↗

board.yamlalp-sdk · v0.17.0

# Same file. Any module.
som:
  sku: E1M-V2N101

preset: e1m-x-evk

cores:
  a55_cluster:
    app:          ./linux
    peripherals:  [ethernet, usb, emmc]
  m33_sm:
    app:          ./m33
    peripherals:  [adc, pwm, i2c, gpio]

running onE1M-X V2N·4 TOPS

See all 5 modules ↗

§ Open source

Built in the open. No NDAs.

The E1M Standard and the Alp SDK live on GitHub underCC BY-SA 4.0 +Apache-2.0. Read the spec, file an issue, send a PR.

View org on GitHub ↗

alplabai/

E1M Standard

Open-standard module pinout, mechanical, electrical spec

Latest commit · 13 d ago

930bebaci: assert STANDARD.md 7.2/7.3.1 prose counts against the pin JSON (#8)

Read the repo ↗

alplabai/

Alp SDK

Unified C/C++ API · heterogeneous build · vendor SDK wrappers

Latest commit · today

7265c8afeat(aen): microSD + FatFs on the E1M-EVK (E4 DT, e1m_evk_microsd shield, SDHC TCM bounce buffer, SD_MMC storage backend, example) (#2869)

Read the repo ↗

§ Silicon partners

Built on industry-leading silicon.

We wrap every vendor's SDK under one C/C++ API on top of Arm CMSIS, so your application code stays the same regardless of which silicon ends up under the module.

Renesas Partner Program

RZ/V2N · V2H · DRP-AI3 on E1M-X

MCU + edge-NPU partner

Ensemble E3–E8 on E1M-AEN

AI accelerator partner

DX-M1 on V2N+M1 and V2H+M1

Long-term silicon commitments. Industrial-grade longevity. Shared roadmaps.

Meet our silicon & channel partners →

§ Authorised distributors